HD64F2149 Datasheet, PDF (213/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SAR or
DAR
Repeat area
Transfer
DAR or
SAR
Figure 7.7 Memory Mapping in Repeat Mode
7.3.7 Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is specified as a block area.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified in the block area is restored. The other address register is
successively incremented or decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested.
Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory
mapping in block transfer mode.
Table 7.7 Register Information in Block Transfer Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Function
Transfer source address
Transfer destination address
Holds block size
Block size count
Transfer counter
179