HD64F2149 Datasheet, PDF (356/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

11.4 Interrupts
The free-running timer can request seven interrupts (three types): input capture A to D (ICIA,
ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 11.4 lists information about these interrupts.
Table 11.4 Free-Running Timer Interrupts
Interrupt
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Description
Requested by ICFA
Requested by ICFB
Requested by ICFC
Requested by ICFD
Requested by OCFA
Requested by OCFB
Requested by OVF
DTC Activation
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Priority
High
Low
11.5 Sample Application
In the example below, the free-running timer is used to generate pulse outputs with a 50% duty
cycle and arbitrary phase relationship. The programming is as follows:
• The CCLRA bit in TCSR is set to 1.
• Each time a compare-match interrupt occurs, software inverts the corresponding output level
bit in TOCR (OLVLA or OLVLB).
H'FFFF
OCRA
OCRB
H'0000
FTOA
FRC
Counter clear
FTOB
322
Figure 11.17 Pulse Output (Example)