HD64F2149 Datasheet, PDF (626/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18B.2.8 Status Registers (STR1, STR2, STR3)
• STR1
Bit
Initial value
Slave Read/Write
Host Read/Write
7
DBU17
0
R/W
R
6
DBU16
0
R/W
R
5
DBU15
0
R/W
R
4
DBU14
0
R/W
R
3
C/D1
0
R
R
2
DBU12
0
R/W
R
1
IBF1
0
R
R
0
OBF1
0
R/(W)*
R
Note: * Only 0 can be written, to clear the flag.
• STR2
Bit
Initial value
Slave Read/Write
Host Read/Write
7
DBU27
0
R/W
R
6
DBU26
0
R/W
R
5
DBU25
0
R/W
R
4
DBU24
0
R/W
R
Note: * Only 0 can be written, to clear the flag.
3
C/D2
0
R
R
2
DBU22
0
R/W
R
1
IBF2
0
R
R
0
OBF2
0
R/(W)*
R
• STR3
Bit
Initial value
Slave Read/Write
Host Read/Write
7
IBF3B
0
R
R
6
5
OBF3B MWMF
0
0
R/(W)* R
R
R
4
SWMF
0
R/(W)*
R
3
C/D3
0
R
R
2
DBU32
0
R/W
R
1
IBF3A
0
R
R
0
OBF3
0
R/(W)*
R
Note: * Only 0 can be written, to clear the flag.
The STR registers are 8-bit registers that indicate status information during host interface
processing. Bits 3, 1, and 0 of STR1 to STR3, and bits 7 to 4 of STR3, are read-only bits to both
the host processor and the slave processor. However, 0 only can be written from the slave
processor to bit 0 of STR1 to STR3, and bits 6 and 4 of STR3, in order to clear the flags to 0. The
registers selected from the host processor according to the I/O address are shown in the following
table. For information on STR3 selection, see section 18B.2.4, LPC Channel 3 Address Register
(LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host
processor.
The STR registers are initialized to H'00 by a reset and in standby mode.
592