HD64F2149 Datasheet, PDF (635/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SIRQCR1 Bit 2—HIRQ10 Interrupt Enable 2 (IRQ10E2): Enables or disables a HIRQ10
interrupt request when OBF2 is set by an ODR2 write.
Bit 2
IRQ10E2
0
1
Description
HIRQ10 interrupt request by OBF2 and IRQ10E2 is disabled
[Clearing conditions]
• Writing 0 to IRQ10E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
[When IEDIR = 0]
HIRQ10 interrupt request by setting OBF2 to 1 is enabled
[When IEDIR = 1]
HIRQ10 interrupt is requested
[Setting condition]
• Writing 1 after reading IRQ10E2 = 0
(Initial value)
SIRQCR1 Bit 1—HIRQ9 Interrupt Enable 2 (IRQ9E2): Enables or disables a HIRQ9 interrupt
request when OBF2 is set by an ODR2 write.
Bit 1
IRQ9E2
0
1
Description
HIRQ9 interrupt request by OBF2 and IRQ9E2 is disabled
[Clearing conditions]
• Writing 0 to IRQ9E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
[When IEDIR = 0]
HIRQ9 interrupt request by setting OBF2 to 1 is enabled
[When IEDIR = 1]
HIRQ9 interrupt is requested
[Setting condition]
• Writing 1 after reading IRQ9E2 = 0
(Initial value)
601