HD64F2149 Datasheet, PDF (570/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 1—Parity Error (PER): Indicates that an odd parity error has occurred.
Bit 1
PER
0
1
Description
[Clearing condition]
Read PER when PER =1, then write 0 in PER
[Setting condition]
When an odd parity error occurs
(Initial value)
Bit 0—Keyboard Stop (KBS): Indicates the receive data stop bit. Valid only when KBF = 1.
Bit 0
KBS
0
1
Description
0 stop bit received
1 stop bit received
(Initial value)
17.2.2 Keyboard Control Register L (KBCRL)
Bit
7
6
5
4
KBE KCLKO KDO
—
Initial value
0
1
1
1
Read/Write R/W R/W R/W
—
3
2
1
0
RXCR3 RXCR2 RXCR1 RXCR0
0
0
0
0
R
R
R
R
KBCRL is an 8-bit readable/writable register that enables the receive counter count and controls
the keyboard buffer controller pin output.
KBCRL is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7—Keyboard Enable (KBE): Enables or disables loading of receive data into the keyboard
data buffer register (KBBR).
Bit 7
KBE
0
1
Description
Loading of receive data into KBBR is disabled
Loading of receive data into KBBR is enabled
(Initial value)
536