HD64F2149 Datasheet, PDF (409/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 1—IHI Signal Level (IHI): Indicates the current level of the IHI signal. Signal source and
phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IHI signal at positive
phase by modifying TCONRI.
Bit 1
IHI
0
1
Description
The IHI signal is low
The IHI signal is high
Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and
phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IVI signal at positive
phase by modifying TCONRI.
Bit 0
IVI
0
1
Description
The IVI signal is low
The IVI signal is high
13.2.5 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13, MSTP12, and MSTP8 bits are set to 1, the 16-bit free-running timer, 8-bit
timer channels 0 and 1, and 8-bit timer channels X and Y and timer connection, respectively, halt
and enter module stop mode. See section 24.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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