HD64F2149 Datasheet, PDF (403/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

13.2.2 Timer Connection Register O (TCONRO)
Bit
Initial value
Read/Write
7
HOE
0
R/W
6
VOE
0
R/W
5
CLOE
0
R/W
4
CBOE
0
R/W
3
HOINV
0
R/W
2
VOINV
0
R/W
1
0
CLOINV CBOINV
0
0
R/W R/W
TCONRO is an 8-bit readable/writable register that controls output signal output, phase inversion,
etc.
TCONRO is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 4—Output Enable (HOE, VOE, CLOE, CBOE): These bits control
enabling/disabling of horizontal synchronization signal (HSYNCO), vertical synchronization
signal (VSYNCO), clamp waveform (CLAMPO), and blanking waveform (CBLANK) output.
When output is disabled, the state of the relevant pin is determined by the port DR and DDR, FRT,
TMR, and PWM settings.
Output enabling/disabling control does not affect the port, FRT, or TMR input functions, but some
FRT and TMR input signal sources are determined by the SCONE bit in TCONRI.
Bit 7
HOE
0
1
Description
The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/
HIRQ1 pin
The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin
(Initial value)
Bit 6
VOE
0
1
Description
The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the P61/FTOA/ (Initial value)
KIN1/CIN1 pin
The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the VSYNCO pin
Bit 5
CLOE
0
1
Description
The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the
P64/FTIC/KIN4/CIN4 pin
The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin
(Initial value)
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