HD64F2149 Datasheet, PDF (906/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

KBCRH0—Keyboard Control Register H0
KBCRH1—Keyboard Control Register H1
KBCRH2—Keyboard Control Register H2
H'FED8
H'FEDC
H'FEE0
Bit
Initial value
Read/Write
7
KBIOE
0
R/W
6
KCLKI
1
R
5
4
3
KDI KBFSEL KBIE
1
1
0
R
R/W
R/W
Keyboard Buffer Controller
Keyboard Buffer Controller
Keyboard Buffer Controller
2
KBF
0
R/(W)*
1
PER
0
R/(W)*
0
KBS
0
R
Keyboard stop
0 “0” stop bit received
1 “1” stop bit received
Parity error
0 [Clearing condition]
Read PER when PER =1,
then write 0 in PER
1 [Setting condition]
When an odd parity error occurs
Keyboard buffer register full
0 [Clearing condition]
Read KBF when KBF =1, then write 0 in KBF
1 [Setting conditions]
• When data has been received normally while
KBFSEL = 1, and has been transferred to
KBBR (keyboard buffer register full flag)
• When a KCLK falling edge has been detected
while KBFSEL = 0 (KCLK interrupt flag)
Keyboard interrupt enable
0 Interrupt requests are disabled
1 Interrupt requests are enabled
Keyboard buffer register full select
0 KBF bit is used as KCLK fall interrupt flag
1 KBF bit is used as keyboard buffer register full flag
Keyboard data in
0 KD I/O pin is low
1 KD I/O pin is high
Keyboard clock in
0 KCLK I/O pin is low
1 KCLK I/O pin is high
Keyboard in/out enable
0 The keyboard buffer controller is non-operational (KCLK and KD signal pins
have port functions)
1 The keyboard buffer controller is enabled for transmission and reception
(KCLK and KD signal pins are in the bus drive state)
Note: * Only 0 can be written, to clear the flag.
872