HD64F2149 Datasheet, PDF (384/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.3.3 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.7 shows the timing of this operation.
ø
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12.7 Timing of Clearing by External Reset Input
12.3.4 Timing of Overflow Flag (OVF) Setting
OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
12.8 shows the timing of this operation.
ø
TCNT
H'FF
Overflow signal
H'00
OVF
Figure 12.8 Timing of OVF Setting
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