HD64F2149 Datasheet, PDF (839/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

A.4 Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8S/2000 CPU. Table A.5 shows the number of instruction fetch, data
read/write, and other cycles occurring in each instruction, and table A.4 shows the number of
states required per cycle according to the bus size. The number of states required for execution of
an instruction can be calculated from these two tables as follows:
Number of states = I × S_I + J × S_J + K × S_K + L × S_L + M × S_M + N × S_N
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed in two states with 8-bit bus width, external devices accessed in three states with one wait
state and 16-bit bus width.
1. BSET #0,@FFFFC7:8
From table A.5, I = L = 2 and J = K = M = N = 0
From table A.4, S_I = 4 and S_L = 2
Number of states = 2 × 4 + 2 × 2 = 12
2. JSR @@30
From table A.5, I = J = K = 2 and L = M = N = 0
From table A.4, S_I = S_J= S_K = 4
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
805