HD64F2149 Datasheet, PDF (430/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF
to H'00.
Bit 7
OVF
Description
0
[Clearing conditions]
• Write 0 in the TME bit
(Initial value)
• Read TCSR when OVF = 1*, then write 0 in OVF
1
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.)
Note: When OVF flag is polled and the interval timer interrupt is disabled, OVF=1 must be read at
last twice.
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI
interrupt when TCNT overflows. When internal reset is selected in watchdog timer mode, a low-
level signal is output from the RESO pin.
Bit 6
WT/IT
0
1
Description
Interval timer mode: Sends the CPU an interval timer interrupt request
(WOVI) when TCNT overflows
(Initial value)
Watchdog timer mode: Generates a reset or NMI interrupt when TCNT
overflows
At the same time, a low-level signal is output from the RESO pin (when
internal reset is selected)
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
0
1
Description
TCNT is initialized to H'00 and halted
TCNT counts
(Initial value)
396