HD64F2149 Datasheet, PDF (163/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.5.5 Interrupt Response Times
The H8S/2149 is capable of fast word access to on-chip memory, and high-speed processing can
be achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM.
Table 5.8 shows interrupt response times—the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols used in table
5.8 are explained in table 5.9.
Table 5.8 Interrupt Response Times
Number of States
No. Item
Normal Mode
Advanced Mode
1 Interrupt priority determination*¹
3
3
2 Number of wait states until executing
instruction ends*²
1 to (19+2·S_I)
1 to (19+2·S_I)
3 PC, CCR stack save
4 Vector fetch
5 Instruction fetch*³
6 Internal processing*⁴
2·S_K
S_I
2·S_I
2
2·S_K
2·S_I
2·S_I
2
Total (using on-chip memory)
11 to 31
12 to 32
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.9 Number of States in Interrupt Handling Routine Execution
Object of Access
External Device
8-Bit Bus
16-Bit Bus
Internal 2-State 3-State
Symbol Memory Access Access
2-State 3-State
Access Access
Instruction fetch
S_I
1
4
6+2m
2
Branch address read S_J
Stack manipulation
S_K
Legend:
m: Number of wait states in an external device access
3+m
129