HD64F2149 Datasheet, PDF (505/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be
accepted in this case.
15.5 Usage Notes
The following points should be noted when using the SCI.
Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
Operation when Multiple Receive Errors Occur Simultaneously
If a number of receive errors occur at the same time, the state of the status flags in SSR is as
shown in table 15.14. If there is an overrun error, data is not transferred from RSR to RDR, and
the receive data is lost.
Table 15.14 State of SSR Status Flags and Transfer of Receive Data
RDRF
1
0
0
1
1
0
1
SSR Status Flags
ORER FER PER
1
0
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
Receive Data Transfer
RSR to RDR
X
O
O
X
X
O
X
Notes: O: Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
Receive Errors
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error +
parity error
471