HD64F2149 Datasheet, PDF (138/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or
both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode.
ISCRH Bits 7 to 0, ISCRL Bits 7 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to
IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB)
ISCRH Bits 7 to 0
ISCRL Bits 7 to 0
IRQ7SCB to IRQ7SCA to
IRQ0SCB
IRQ0SCA
0
0
1
1
0
1
Description
Interrupt request generated at IRQ7 to IRQ0 input low level
(Initial value)
Interrupt request generated at falling edge of IRQ7 to IRQ0 input
Interrupt request generated at rising edge of IRQ7 to IRQ0 input
Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input
5.2.5 IRQ Status Register (ISR)
Bit
Initial value
Read/Write
7
IRQ7F
0
R/(W)*
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
Note: * Only 0 can be written, to clear the flag.
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
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