HD64F2149 Datasheet, PDF (549/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Slave receive mode Slave transmit mode
SCL
(master output) 8
9
SCL
(slave output)
1
2
3
4
5
6
7
8
9
1
2
SDA
(slave output)
A
SDA
[2]
(master output) _R/W
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
Bit 7 Bit 6
Data 2
A
TDRE
IRIC
ICDRT
Interrupt
request
generation
Interrupt
request
generation
Data 1
Data 2
[3]
Interrupt
request
generation
ICDRS
Data 1
Data 2
User processing
[3] IRIC
[3] ICDR write
clearance
[3] ICDR write
[5] IRIC
[5] ICDR write
clearance
Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0)
16.3.6 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 16.11 shows the IRIC set timing and SCL control.
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