HD64F2149 Datasheet, PDF (678/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

20.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 20.5 shows the A/D
conversion timing. Table 20.4 indicates the A/D conversion time.
As indicated in figure 20.5, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 20.4.
In scan mode, the values given in table 20.4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
ø
Address
(2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
t _CONV
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t_D: A/D conversion start delay
t_SPL: Input sampling time
t_CONV: A/D conversion time
Figure 20.5 A/D Conversion Timing
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