HD64F2149 Datasheet, PDF (598/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18A.2.7 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP2 bit is set to 1, the host interface (HIF:XBS) halts and enters module stop mode.
See section 24.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface (HIF:XBS) module stop
mode.
MSTPCRL
Bit 2
MSTP2
0
1
Description
Host interface (HIF: XBS) module stop mode is cleared
Host interface (HIF: XBS) module stop mode is set
(Initial value)
18A.3 Operation
18A.3.1 Host Interface Activation
The host interface is activated by setting the HI12E bit (bit 0) in SYSCR2 to 1 in single-chip
mode. When the host interface is activated, all related I/O ports (data port 3, control ports 8 and 9,
and host interrupt request port 4) become dedicated host interface ports. Setting the CS3E bit and
CS4E bit to 1 enables the number of host interface channels to be extended to a four, and makes
the channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a
dedicated host interface port.
Table 18A.4 shows HIF host interface channel selection and pin operation.
564