HD64F2149 Datasheet, PDF (516/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TDRE
0
1
RDRF
0
1
Description
The next transmit data is in ICDR (ICDRT), or transmission cannot
be started
(Initial value)
[Clearing conditions]
• When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1)
• When a stop condition is detected in the bus line state after a stop condition is
issued with the I²C bus format or serial format selected
• When a stop condition is detected with the I²C bus format selected
• In receive mode (TRS = 0)
(A 0 write to TRS during transfer is valid after reception of a frame containing an
acknowledge bit)
The next transmit data can be written in ICDR (ICDRT)
[Setting conditions]
• In transmit mode (TRS = 1), when a start condition is detected in the bus line state
after a start condition is issued in master mode with the I²C bus format or serial
format selected
• At the first transmit mode setting (TRS = 1) (first transmit mode setting only) after
I²C bus mode is switched to formatless mode
• When data is transferred from ICDRT to ICDRS
(Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is
empty)
• When receive mode (TRS = 0) is switched to transmit mode (TRS = 1 ) after
detection of a start condition (first transmit mode setting only)
Description
The data in ICDR (ICDRR) is invalid
(Initial value)
[Clearing condition]
When ICDR (ICDRR) receive data is read in receive mode
The ICDR (ICDRR) receive data can be read
[Setting condition]
When data is transferred from ICDRS to ICDRR
(Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and
RDRF = 0)
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