HD64F2149 Datasheet, PDF (218/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 7.9 Number of States Required for Each Execution Phase
Object of Access
Bus width
Access states
Execution Vector read
S_I
phase
Register
S_J
information
read/write
Byte data read S_K
Word data read S_K
Byte data write S_L
Word data write S_L
Internal operation S_M
On- On-
Chip Chip Internal I/O
RAM ROM Registers External Devices
32 16 8
16 8
8
16
1
1
2
2
2
3
2
—1
——4
6+2m 2
1
—————
—
1
1
2
2
2
3+m 2
1
1
4
2
4
6+2m 2
1
1
2
2
2
3+m 2
1
1
4
2
4
6+2m 2
1
1
1
1
1
1
1
16
3
3+m
—
3+m
3+m
3+m
3+m
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number for which the CHNE bit is set to one,
plus 1).
Number of execution states = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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