HD64F2149 Datasheet, PDF (688/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

21.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 21.1 shows the register configuration.
Table 21.1 Register Configuration
Name
Abbreviation R/W
System control register
SYSCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'09
Address*
H'FFC4
21.2 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
2
NMIEG
0
R/W
1
HIE
0
R/W
0
RAME
1
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
654