HD64F2149 Datasheet, PDF (139/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit n
IRQnF
0
Description
[Clearing conditions]
(Initial value)
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt exception handling is executed while low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high*
• When IRQn interrupt exception handling is executed while falling, rising, or both-edge
detection is set (IRQnSCB = 1 or IRQnSCA = 1)*
1
[Setting conditions]
• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
• When a falling edge occurs in IRQn input while falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input while rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input while both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
Note:
(n = 7 to 0)
* When a product, in which a DTC is incorporated, is used in the following settings, the
corresponding flag bit is not automatically cleared even when exception handing, which
is a clear condition, is executed and the bit is held at 1.
(1) When DTCEA3 is set to 1(ADI is set to an interrupt source), of IRQ4F flag is not
automatically cleared.
(2) When DTCEA2 is set to 1(ICIA is set to an interrupt source), clearing of IRQ5F flag
is not automatically cleared.
(3) When DTCEA1 is set to 1(ICIB is set to an interrupt source), clearing of IRQ6F flag
is not automatically cleared.
(4) When DTCEA0 is set to 1(OCIA is set to an interrupt source), clearing of IRQ7F
flag is not automatically cleared.
When activation interrupt sources of DTC and IRQ interrupts are used with the above
combinations, clear the interrupt flag by software in the interrupt handling routine of the
corresponding IRQ.
5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0
1
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
KMIMR is an 8-bit readable/writable register that performs mask control for the keyboard matrix
interrupt inputs (pins KIN7 to KIN0) and pin IRQ6. To enable key-sense input interrupts from
multiple pin inputs in keyboard matrix scanning/sensing, clear the corresponding mask bits to 0.
105