HD64F2149 Datasheet, PDF (747/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Reset state
STBY pin = high
RES pin = low
RES pin = high
Program execution state
High-speed
mode
(main clock)
SLEEP
instruction
Any interrupt^*3
SCK2 to SCK2 to
SCK0 = 0 SCK0 ≠ 0
SLEEP
instruction
Medium-speed
mode
(main clock)
External
interrupt^*4
SLEEP
instruction
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
Clock switching
exception handling
after oscillation
setting time
(STS2 to STS0)
SLEEP instruction
Interrupt^*1,
SSBY = 1, PSS = 1, ^{LSON bit = 0}
DTON = 1, LSON = 1
Clock switching
exception handling
SLEEP
instruction
Interrupt^*1,
LSON bit = 1
Subactive mode
(subclock)
SLEEP instruction
Interrupt^*2
Program-halted state
STBY pin = low
Hardware
standby mode
SSBY = 0, LSON = 0
Sleep mode
(main clock)
SSBY = 1
PSS = 0, LSON = 0
Software
standby mode
SSBY = 1
PSS = 1, DTON = 0
Watch mode
(subclock)
SSBY = 0
PSS = 1, LSON = 1
Subsleep mode
(subclock)
: Transition after exception handling
: Power-down mode
Notes: • When a transition is made between modes by means of an interrupt, transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting
the interrupt request.
• From any state except hardware standby mode, a transition to the reset state occurs whenever
RES goes low.
• From any state, a transition to hardware standby mode occurs when STBY goes low.
• When a transition is made to watch mode or subactive mode, high-speed mode must be set.
*1 NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts
*2 NMI, IRQ0 to IRQ7, and WDT0 interrupts, WDT1 interrupt, TMR0 interrupt, TMR1 interrupt
*3 All interrupts
*4 NMI, IRQ0 to IRQ2, IRQ6, IRQ7
Figure 24.1 Mode Transitions
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