HD64F2149 Datasheet, PDF (433/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• WDT1 input clock selection
Bit 4 Bit 2 Bit 1 Bit 0
Description
PSS
0
CKS2
0
CKS1
0
CKS0
0
Clock
Overflow Period* (when ø = 10 MHz
and ø_SUB = 32.768 kHz)
ø/2 (Initial value) 51.2 µs
1
ø/64
1.6 ms
1
0
ø/128
3.2 ms
1
ø/512
13.1 ms
1
0
0
ø/2048
52.4 ms
1
ø/8192
209.7 ms
1
0
ø/32768
838.9 ms
1
ø/131072
3.36 s
1
0
0
0
øSUB/2
15.6 ms
1
øSUB/4
31.3 ms
1
0
øSUB/8
62.5 ms
1
øSUB/16
125 ms
1
0
0
øSUB/32
250 ms
1
øSUB/64
500 ms
1
0
øSUB/128
1s
1
øSUB/256
2s
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow
occurs.
14.2.3 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
CS2E
0
R/W
6
5
4
3
2
1
0
IOSE INTM1 INTM0 XRST NMIEG HIE RAME
0
0
0
1
0
0
1
R/W
R
R/W
R
R/W R/W R/W
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
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