HD64F2149 Datasheet, PDF (534/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16.2.7 Serial/Timer Control Register (STCR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the I²C interface operating
mode (when the on-chip IIC option is included), and on-chip flash memory, and selects the TCNT
input clock source. For details of functions not related to the I²C bus interface, see section 3.2.4,
Serial/Timer Control Register (STCR), and the descriptions of the relevant modules. If a module
controlled by STCR is not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—I²C Extra Buffer Select (IICS): Designates bits 7 to 4 of port A as the same kind of
output buffer as SCL and SDA. This bit is used when implementing the I²C interface by software
only.
Bit 7
IICS
0
1
Description
PA7 to PA4 are normal I/O pins
PA7 to PA4 are I/O pins with bus driving capability
(Initial value)
Bit 6—I²C Transfer Select 1 (IICX1): This bit, together with bits CKS2 to CKS0 in ICMR of
IIC1, selects the transfer rate in master mode. For details, see section 16.2.4, I²C Bus Mode
Register (ICMR).
Bit 5—I²C Transfer Select 0 (IICX0): This bit, together with bits CKS2 to CKS0 in ICMR of
IIC0, selects the transfer rate in master mode. For details, see section 16.2.4, I²C Bus Mode
Register (ICMR).
Bit 4—I²C Master Enable (IICE): Controls CPU access to the I²C bus interface data and control
registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).
Bit 4
IICE
0
1
Description
CPU access to I²C bus interface data and control registers is disabled
CPU access to I²C bus interface data and control registers is enabled
(Initial value)
500