HD64F2149 Datasheet, PDF (969/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TCSR1—Timer Control/Status Register 1
H'FFEA
TCSR1
Bit
Initial value
Read/Write
7
OVF
0
R/(W)^*1
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
2
RST/NMI CKS2
0
0
R/W R/W
1
CKS1
0
R/W
WDT1
0
CKS0
0
R/W
Clock select 2 to 0
PSS CKS2 CKS1 CKS0
Clock
0
0
0
0 ø/2
1 ø/64
1
0 ø/128
1 ø/512
1
0
0 ø/2048
1 ø/8192
1
0 ø/32768
1 ø/131072
1
0
0
0 øSUB/2
1 øSUB/4
1
0 øSUB/8
1 øSUB/16
1
0
0 øSUB/32
1 øSUB/64
1
0 øSUB/128
1 øSUB/256
Reset or NMI
0 NMI interrupt requested
1 Internal reset requested
Prescaler select^*2
0 TCNT counts on a ø-based prescaler (PSM) divided clock pulses
1 TCNT counts on a øSUB-based prescaler (PSS) divided clock pulses
Timer enable
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Timer mode select
0 Interval timer mode: Interval timer interrupt request (WOVI) sent to CPU
when TCNT overflows
1 Watchdog timer mode: Reset or NMI interrupt request sent to CPU when
TCNT overflows
RESO pin output goes low simultaneously (when internal reset is selected)
Overflow flag
0 [Clearing conditions]
• When 0 is written in the TME bit
• When 0 is written in OVF after reading TCSR when OVF = 1
1 [Setting condition]
When TCNT overflows from H'FF to H'00
When internal reset request is selected in watchdog timer mode, OVF is cleared
automatically by an internal reset after being set
Notes: 1. Only 0 can be written, to clear the flag.
2. For operation control when a transition is made to power-down mode, see section 24.2.3, Timer Control/Status Register (TCSR).
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