HD64F2149 Datasheet, PDF (613/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

HICR0 Bits 7 to 5—LPC Enable 3 to 1 (LPC3E, LPC2E, LPC1E): These bits enable or disable
the host interface function in single-chip mode. When the host interface is enabled (at least one of
the three bits is set to 1), processing for data transfer between the slave processor and the host
processor is performed using pins LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ,
CLKRUN, and LPCPD.
HICR0
Bit 7
LPC3E
0
1
Description
LPC channel 3 operation is disabled
(Initial value)
No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15
LPC channel 3 operation is enabled
HICR0
Bit 6
LPC2E
0
1
Description
LPC channel 2 operation is disabled
No address (H'0062, 66) matches for IDR2, ODR2, or STR2
LPC channel 2 operation is enabled
(Initial value)
HICR0
Bit 5
LPC1E
0
1
Description
LPC channel 1 operation is disabled
No address (H'0060, 64) matches for IDR1, ODR1, or STR1
LPC channel 1 operation is enabled
(Initial value)
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