HD64F2149 Datasheet, PDF (136/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)
Bit
Initial value
Read/Write
7
ICR7
0
R/W
6
ICR6
0
R/W
5
ICR5
0
R/W
4
ICR4
0
R/W
3
ICR3
0
R/W
2
ICR2
0
R/W
1
ICR1
0
R/W
0
ICR0
0
R/W
The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for
interrupts other than NMI and address break.
The correspondence between ICR settings and interrupt sources is shown in table 5.3.
The ICR registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—Interrupt Control Level (ICRn): Sets the control level for the corresponding interrupt
source.
Bit n
ICRn
0
1
Description
Corresponding interrupt source is control level 0 (non-priority)
Corresponding interrupt source is control level 1 (priority)
(Initial value)
(n = 7 to 0)
Table 5.3 Correspondence between Interrupt Sources and ICR Settings
Bits
Register 7
6
5
4
3
2
1
0
ICRA
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
DTC
Watchdog Watchdog
timer 0 timer 1
ICRB A/D
Free- —
—
8-bit
8-bit
8-bit
HIF:XBS
converter running
timer
timer
timer
Keyboard
timer
channel 0 channel 1 channels buffer
X, Y
controller
ICRC
SCI
SCI
SCI
IIC
IIC
—
channel 0 channel 1 channel 2 channel 0 channel 1
HIF:LPC —
102