HD64F2149 Datasheet, PDF (486/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Initialization
Start transmission
Read TDRE flag in SSR
No
TDRE = 1?
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
Yes
[1] ^{[1] SCI initialization:}
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, one
[2]
frame of 1s is output and
transmission is enabled.
[2] _{SCI status check and transmit}
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] _{Serial transmission continuation}
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmit-
data-empty interrupt (TXI)
request, and data is written to
TDR.
[4] _{Break output at the end of serial}
transmission:
To output a break in serial
transmission, set the port DDR to
[4]
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 15.10 Sample Multiprocessor Serial Transmission Flowchart
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