HD64F2149 Datasheet, PDF (26/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.1.4 Register Configuration.......................................................................................... 394
14.2 Register Descriptions......................................................................................................... 394
14.2.1 Timer Counter (TCNT) ........................................................................................ 394
14.2.2 Timer Control/Status Register (TCSR) ................................................................ 395
14.2.3 System Control Register (SYSCR) ...................................................................... 399
14.2.4 Notes on Register Access ..................................................................................... 400
14.3 Operation ........................................................................................................................... 401
14.3.1 Watchdog Timer Operation.................................................................................. 401
14.3.2 Interval Timer Operation...................................................................................... 402
14.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 403
14.3.4 RESO Signal Output Timing................................................................................ 404
14.4 Interrupts............................................................................................................................ 404
14.5 Usage Notes ....................................................................................................................... 405
14.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 405
14.5.2 Changing Value of CKS2 to CKS0...................................................................... 405
14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 405
14.5.4 System Reset by RESO Signal............................................................................. 406
14.5.5 Counter Value in Transitions between High-Speed Mode, Subactive Mode,
and Watch Mode .................................................................................................. 406
14.5.6 OVF Flag Clear Condition ................................................................................... 407
Section 15 Serial Communication Interface (SCI, IrDA)........................................ 409
15.1 Overview............................................................................................................................ 409
15.1.1 Features ................................................................................................................ 409
15.1.2 Block Diagram...................................................................................................... 411
15.1.3 Pin Configuration ................................................................................................. 412
15.1.4 Register Configuration ......................................................................................... 412
15.2 Register Descriptions......................................................................................................... 414
15.2.1 Receive Shift Register (RSR)............................................................................... 414
15.2.2 Receive Data Register (RDR) .............................................................................. 414
15.2.3 Transmit Shift Register (TSR).............................................................................. 415
15.2.4 Transmit Data Register (TDR) ............................................................................. 415
15.2.5 Serial Mode Register (SMR)................................................................................ 416
15.2.6 Serial Control Register (SCR).............................................................................. 418
15.2.7 Serial Status Register (SSR)................................................................................. 422
15.2.8 Bit Rate Register (BRR)....................................................................................... 426
15.2.9 Serial Interface Mode Register (SCMR) .............................................................. 433
15.2.10 Module Stop Control Register (MSTPCR) .......................................................... 434
15.2.11 Keyboard Comparator Control Register (KBCOMP) .......................................... 435
15.3 Operation ........................................................................................................................... 437
15.3.1 Overview .............................................................................................................. 437
15.3.2 Operation in Asynchronous Mode........................................................................ 439
15.3.3 Multiprocessor Communication Function............................................................ 450
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