HD64F2149 Datasheet, PDF (705/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

The flash memory block configuration is shown in table 22.6.
Table 22.6 Flash Memory Erase Blocks
Block (Size)
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbytes)
EB4 (28 kbytes)
EB5 (16 kbytes)
EB6 (8 kbytes)
EB7 (8 kbytes)
Address
H'(00)0000 to H'(00)03FF
H'(00)0400 to H'(00)07FF
H'(00)0800 to H'(00)0BFF
H'(00)0C00 to H'(00)0FFF
H'(00)1000 to H'(00)7FFF
H'(00)8000 to H'(00)BFFF
H'(00)C000 to H'(00)DFFF
H'00E000 to H'00FFFF
22.5.4 Serial/Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
IICS IICX1 IICX0
IICE FLSHE
—
ICKS1 ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory, and also selects the TCNT
input clock. For details on functions not related to on-chip flash memory, see section 3.2.4,
Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module
controlled by STCR is not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4—I²C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the
I²C bus interface. For details, see section 16, I²C Bus Interface.
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