HD64F2149 Datasheet, PDF (327/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

10.4 Operation
A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS =
0, the value in DADR corresponds to the total width (T_L) of the low (0) pulses output in one
conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output
waveform is inverted and the DADR value corresponds to the total width (T_H) of the high (1)
output pulses. Figure 10.4 shows the types of waveform output available.
t_f
Basic cycle
(T × 64 or T × 256)
1 conversion cycle
(T × 2¹⁴ (= 16384))
t_L
T: Resolution
m
T_L = ∑ t_Ln (when OS = 0)
n=1
(When CFS = 0, m = 256; when CFS = 1, m = 64)
Figure 10.3 PWM D/A Operation
Table 10.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,
base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a
certain minimum value. Table 10.4 indicates the range of DADR settings that give an output
waveform like the one in figure 10.3, and lists the conversion cycle length when low-order DADR
bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
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