HD64F2149 Datasheet, PDF (178/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Byte size
Upper data bus Lower data bus
D15
D8 D7
D0
Word size
1st bus cycle
2nd bus cycle
Longword size
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Byte size
Byte size
• Even address
• Odd address
Upper data bus
Lower data bus
D15
D8 D7
D0
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space)
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