HD64F2149 Datasheet, PDF (370/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 7—Compare-Match Interrupt Enable B (CMIEB): Selects whether the CMFB interrupt
request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Note that a CMIB interrupt is not requested by TMRX, regardless of the CMIEB value.
Bit 7
CMIEB
0
1
Description
CMFB interrupt request (CMIB) is disabled
CMFB interrupt request (CMIB) is enabled
(Initial value)
Bit 6—Compare-Match Interrupt Enable A (CMIEA): Selects whether the CMFA interrupt
request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1.
Note that a CMIA interrupt is not requested by TMRX, regardless of the CMIEA value.
Bit 6
CMIEA
0
1
Description
CMFA interrupt request (CMIA) is disabled
CMFA interrupt request (CMIA) is enabled
(Initial value)
Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request
(OVI) is enabled or disabled when the OVF flag in TCSR is set to 1.
Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value.
Bit 5
OVIE
0
1
Description
OVF interrupt request (OVI) is disabled
OVF interrupt request (OVI) is enabled
(Initial value)
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select the method by which
the timer counter is cleared: by compare-match A or B, or by an external reset input.
Bit 4
CCLR1
0
1
Bit 3
CCLR0
0
1
0
1
Description
Clearing is disabled
Cleared on compare-match A
Cleared on compare-match B
Cleared on rising edge of external reset input
(Initial value)
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