HD64F2149 Datasheet, PDF (66/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• High-speed operation
 All frequently-used instructions execute in one or two states
 Maximum clock rate:
10 MHz
 8/16/32-bit register-register add/subtract: 100 ns
 8 × 8-bit register-register multiply:
1200 ns
 16 ÷ 8-bit register-register divide:
1200 ns
 16 × 16-bit register-register multiply: 2000 ns
 32 ÷ 16-bit register-register divide:
2000 ns
• Two CPU operating modes
 Normal mode
 Advanced mode
• Power-down state
 Transition to power-down state by SLEEP instruction
 CPU clock speed selection
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions differ as follows.
Instruction
MULXU
MULXS
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
Number of Execution States
H8S/2600
H8S/2000
3
12
4
20
4
13
5
21
There are also differences in the address space, EXR register functions, power-down state, etc.,
depending on the product.
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