HD64F2149 Datasheet, PDF (450/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.2.5 Serial Mode Register (SMR)
Bit
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E STOP MP CKS1 CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W R/W
R/W R/W R/W
R/W R/W
SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate
generator clock source.
SMR can be read or written to by the CPU at all times.
SMR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the
SCI operating mode.
Bit 7
C/A
0
1
Description
Asynchronous mode
Synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR
Description
0
8-bit data
(Initial value)
1
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSB-first/MSB-
first selection is not available.
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, or when a
multiprocessor format is used, parity bit addition and checking is not performed, regardless of the
PE bit setting.
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