HD64F2149 Datasheet, PDF (350/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

11.3.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
ø
Compare-match A
signal
FRC
N
H'0000
Figure 11.6 Clearing of FRC by Compare-Match A
11.3.4 Input Capture Input Timing
Input Capture Input Timing: An internal input capture signal is generated from the rising or
falling edge of the signal at the input capture pin, as selected by the corresponding IEDGx (x = A
to D) bit in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is
selected (IEDGx = 1).
ø
Input capture
input pin
Input capture
signal
Figure 11.7 Input Capture Signal Timing (Usual Case)
If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal
arrives, the internal input capture signal is delayed by one system clock (ø) period. Figure 11.8
shows the timing for this case.
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