HD64F2149 Datasheet, PDF (959/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TCR0—Timer Control Register 0
TCR1—Timer Control Register 1
TCRX—Timer Control Register X
TCRY—Timer Control Register Y
H'FFC8
H'FFC9
H'FFF0
H'FFF0
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
3
CCLR1 CCLR0
0
0
R/W R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
TMR0
TMR1
TMRX
TMRY
0
CKS0
0
R/W
Counter clear 1 and 0
0 0 Clear is disabled
1 Cleared on compare
match A
1 0 Cleared on compare
match B
1 Cleared on rising edge
of external reset input
Timer overflow interrupt enable
0 OVF interrupt request (OVI) is disabled
1 OVF interrupt request (OVI) is enabled
Compare match interrupt enable A
0 CMFA interrupt request (CMIA) is disabled
1 CMFA interrupt request (CMIA) is enabled
Compare Match Interrupt Enable B
0 CMFB interrupt request (CMIB) is disabled
1 CMFB interrupt request (CMIB) is enabled
Clock select 2 to 0
Bit 2 Bit 1 Bit 0
Channel
CKS2 CKS1 CKS0
Description
0
0
0
0 Clock input disabled
1^*1 Internal clock: counting at falling edge of ø/8
Internal clock: counting at falling edge of ø/2
1
0^*1 Internal clock: counting at falling edge of ø/64
Internal clock: counting at falling edge of ø/32
1^*1 Internal clock: counting at falling edge of ø/1024
Internal clock: counting at falling edge of ø/256
1
0
0 Counting at TCNT1 overflow signal^*2
1
0
0
0 Clock input disabled
1^*1 Internal clock: counting at falling edge of ø/8
Internal clock: counting at falling edge of ø/2
1
0^*1 Internal clock: counting at falling edge of ø/64
Internal clock: counting at falling edge of ø/128
1*¹ Internal clock: counting at falling edge of ø/1024
Internal clock: counting at falling edge of ø/2048
1
0
0 Count at TCNT0 compare match A^*2
X
0
0
0 Clock input disabled
1 Internal clock: counting on ø
1
0 Internal clock: counting at falling edge of ø/2
1 Internal clock: counting at falling edge of ø/4
1
0
0 Clock input disabled
Y
0
0
0 Clock input disabled
1 Internal clock: counting at falling edge of ø/4
1
0 Internal clock: counting at falling edge of ø/256
1 Internal clock: counting at falling edge of ø/2048
1
0
0 Clock input disabled
All
1
0
1 External clock: counting at rising edge
1
0 External clock: counting at falling edge
1 External clock: counting at both rising and falling
edges
Notes: 1. Selected by ICKS1 and ICKS0 in STCR. For details, see section 12.2.4,
Timer Control Register (TCR).
2. If the clock input of channel 0 is the TCNT1 overflow signal and that of
channel 1 is the TCNT0 compare match signal, no incrementing clock is
generated. Do not use this setting.
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