HD64F2149 Datasheet, PDF (202/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

7.2.6 DTC Transfer Count Register B (CRB)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde-Unde- Unde- Unde-
fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
Read/Write — — — — — — — — — — — — — — — —
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
7.2.7 DTC Enable Registers (DTCER)
Bit
Initial value
Read/Write
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
0
DTCE0
0
R/W
The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
0
1
Description
DTC activation by interrupt is disabled
(Initial value)
[Clearing conditions]
• When data transfer ends with the DISEL bit set to 1
• When the specified number of transfers end
DTC activation by interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
(n = 7 to 0)
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number
generated by the interrupt controller in each case.
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