HD64F2149 Datasheet, PDF (801/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
Test
Symbol Min
Typ
Max Unit Condition
Erase
Wait time after x
SWE-bit setting*¹
1
—
—
µs
Wait time after y
ESU-bit setting*¹
100
—
—
µs
Wait time after z
E-bit setting*^1,*⁶
10
—
100
ms
Wait time after α
E-bit clear*¹
10
—
—
µs
Wait time after β
ESU-bit clear*¹
10
—
—
µs
Wait time after γ
EV-bit setting*¹
20
—
—
µs
Wait time after ε
dummy write*¹
2
—
—
µs
Wait time after η
EV-bit clear*¹
4
—
—
µs
Wait time after θ
SWE-bit clear *¹
100
—
—
µs
Maximum erase N
count*^1,*^6,*⁷
—
—
120
Times
Notes: 1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1
is set. It does not include the programming verification time.)
3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximum programming time (tP (max))
tP (max) = (wait time after P-bit setting (z1) + (z3)) × 6
+ wait time after P-bit setting (z2) × ((N) – 6)
5. The maximun number of writes (N) should be set according to the actual set value of
z1, z2 and z3 to allow programming within the maximum programming time (tP (max)).
The wait time after P-bit setting (z1,z2, and z3) should be alternated according to the
number of writes (n) as follows:
1 ≤ n≤ 6
z1 = 30µs, z3 = 10µs
7 ≤ n ≤ 1000 z2 = 200µs
6. Maximum erase time (tE (max))
tE (max) = Wait time after E-bit setting (z) × maximum erase count (N)
7. The maximum number of erases (N) should be set according to the actual set value of z
to allow erasing within the maximum erase time (tE (max)).
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