HD64F2149 Datasheet, PDF (557/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Slave transmit mode
Clear IRIC in ICCR
Write transmit data in ICDR
[1]
[1] Set transmit data for the second and
subsequent bytes.
Clear IRIC in ICCR
[2] Wait for 1 byte to be transmitted.
[3] Test for end of transfer.
Read IRIC in ICCR
No
IRIC = 1?
[4] Select slave receive mode.
[5] Dummy read (to release the SCL line).
[2]
Yes
Read ACKB in ICSR
[3]
End
No
of transmission
(ACKB = 1)?
Yes
Set TRS = 0 in ICCR
[4]
Read ICDR
[5]
Clear IRIC in ICCR
End
Figure 16.17 Flowchart for Slave Transmit Mode (Example)
16.3.11 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in the DDCSWR
register or clearing ICE bit. For details the setting of bits CLR3 to CLR0, see section 16.2.8, DDC
Switch Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
• TDRE and RDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
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