HD64F2149 Datasheet, PDF (898/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SIRQCR1—SERIRQ Control Register 1
H'FE37
HIF (LPC)
Bit
7
6
5
4
3
2
1
0
IRQ11E3 IRQ10E3 IRQ9E3 IRQ6E3 IRQ11E2 IRQ10E2 IRQ9E2 IRQ6E2
Initial value
0
0
0
0
0
0
0
0
Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Host Read/Write
—
—
—
—
—
—
—
—
HIRQ6 interrupt enable 2
0 HIRQ6 interrupt request by OBF2 and IRQ6E2 is disabled
[Clearing conditions] • Writing 0 to IRQ6E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
1 [When IEDIR = 0]
[When IEDIR = 1]
[Setting condition]
HIRQ6 interrupt request by setting OBF2 to 1 is enabled
HIRQ6 interrupt is requested
• Writing 1 after reading IRQ6E2 = 0
HIRQ9 interrupt enable 2
0 HIRQ9 interrupt request by OBF2 and IRQ9E2 is disabled
[Clearing conditions] • Writing 0 to IRQ9E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
1 [When IEDIR = 0]
[When IEDIR = 1]
[Setting condition]
HIRQ9 interrupt request by setting OBF2 to 1 is enabled
HIRQ9 interrupt is requested
• Writing 1 after reading IRQ9E2 = 0
HIRQ10 interrupt enable 2
0 HIRQ10 interrupt request by OBF2 and IRQ10E2 is disabled
[Clearing conditions] • Writing 0 to IRQ10E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
1 [When IEDIR = 0]
[When IEDIR = 1]
[Setting condition]
HIRQ10 interrupt request by setting OBF2 to 1 is enabled
HIRQ10 interrupt is requested
• Writing 1 after reading IRQ10E2 = 0
HIRQ11 interrupt enable 2
0 HIRQ11 interrupt request by OBF2 and IRQ11E2 is disabled
[Clearing conditions] • Writing 0 to IRQ11E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
1 [When IEDIR = 0]
[When IEDIR = 1]
[Setting condition]
HIRQ11 interrupt request by setting OBF2 to 1 is enabled
HIRQ11 interrupt is requested
• Writing 1 after reading IRQ11E2 = 0
HIRQ6 interrupt enable 3
0 HIRQ6 interrupt request by OBF3A and IRQ6E3 is disabled
[Clearing conditions] • Writing 0 to IRQ6E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
1 [When IEDIR = 0]
[When IEDIR = 1]
[Setting condition]
HIRQ6 interrupt request by setting OBF3A to 1 is enabled
HIRQ6 interrupt is requested
• Writing 1 after reading IRQ6E3 = 0
HIRQ9 interrupt enable 3
0 HIRQ9 interrupt request by OBF3A and IRQ9E3 is disabled
[Clearing conditions] • Writing 0 to IRQ9E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
1 [When IEDIR = 0]
[When IEDIR = 1]
[Setting condition]
HIRQ9 interrupt request by setting OBF3A to 1 is enabled
HIRQ9 interrupt is requested
• Writing 1 after reading IRQ9E3 = 0
HIRQ10 interrupt enable 3
0 HIRQ10 interrupt request by OBF3A and IRQ10E3 is disabled
[Clearing conditions] • Writing 0 to IRQ10E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
1 [When IEDIR = 0]
[When IEDIR = 1]
[Setting condition]
HIRQ10 interrupt request by setting OBF3A to 1 is enabled
HIRQ10 interrupt is requested
• Writing 1 after reading IRQ10E3 = 0
HIRQ11 interrupt enable 3
0 HIRQ11 interrupt request by OBF3A and IRQ11E3 is disabled
[Clearing conditions] • Writing 0 to IRQ11E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
1 [When IEDIR = 0]
[When IEDIR = 1]
[Setting condition]
HIRQ11 interrupt request by setting OBF3A to 1 is enabled
HIRQ11 interrupt is requested
• Writing 1 after reading IRQ11E3 = 0
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