HD64F2149 Datasheet, PDF (637/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SIRQCR0 Bit 0—HIRQ1 Interrupt Enable 1 (IRQ1E1): Enables or disables a HIRQ1 interrupt
request when OBF1 is set by an ODR1 write.
Bit 0
IRQ1E1
0
1
Description
HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled
[Clearing conditions]
• Writing 0 to IRQ1E1
• LPC hardware reset, LPC software reset
• Clearing OBF1 to 0
HIRQ1 interrupt request by setting OBF1 to 1 is enabled
[Setting condition]
• Writing 1 after reading IRQ1E1 = 0
(Initial value)
18B.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP0 bit is set to 1, the host interface (HIF: LPC) halts and enters module stop mode.
See section 24.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 0—Module Stop (MSTP0): Specifies host inteface (HIF:LPC) module stop
mode.
MSTPCRL
Bit 0
MSTP0
0
1
Description
HIF:LPC module stop mode is cleared
HIF:LPC module stop mode is set
(Initial value)
603