HD64F2149 Datasheet, PDF (1030/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
E.1 Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown in figure E.1. RES must
remain low until STBY signal goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
RES
t₁ ≥ 10t_cyc
t₂ ≥ 0 ns
Figure E.1 Timing of Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
not need to be retained, RES does not have to be driven low as in (1).
E.2 Timing of Recovery from Hardware Standby Mode
Drive the RES signal low at least 100 ns before STBY goes high to execute a reset.
STBY
RES
t ≥ 100 ns
t_OSC1
Figure E.2 Timing of Recovery from Hardware Standby Mode
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