HD64F2149 Datasheet, PDF (553/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16.3.9 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.12 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or
SDA input
signal
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Internal
SCL or
SDA
signal
Sampling
clock
System clock
period
Figure 16.13 Block Diagram of Noise Canceler
16.3.10 Sample Flowcharts
Figures 16.13 to 16.16 show sample flowcharts for using the I²C bus interface in each mode.
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