HD64F2149 Datasheet, PDF (413/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

IHI signal
CL1 signal
CL2 signal
TCNT
TCORA
Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)
IHI signal
CL3 signal
TCNT
TICR+TCORC
TICR
Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal)
13.3.3 Measurement of 8-Bit Timer Divided Waveform Period
The timer connection facility, TMR1, and the free-running timer (FRT) can be used to measure the
period of an IHI signal divided waveform. Since TMR1 can be cleared by a rising edge of the
external reset signal (Inverse of the IVI signal), the rise and fall of the IHI signal divided
waveform can be virtually synchronized with the IVI signal. This enables period measurement to
be carried out efficiently.
To measure the period of an IHI signal divided waveform, TCNT in TMR1 is set to count the
external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal
(Inverse of the IVI signal). The value to be used as the division factor is written in TCORA, and
the TMO output method is specified by the OS bits in TCSR. Examples of TCR and TCSR
settings are shown in table 13.5, and the timing chart for measurement of the IVI signal and IHI
signal divided waveform periods is shown in figure 13.5. The period of the IHI signal divided
waveform is given by (ICRD(3) – ICRD(2)) × the resolution.
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