HD64F2149 Datasheet, PDF (421/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

13.3.7 HSYNCO Output
With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of
modification varies according to the IHI signal source and the waveform required by external
circuitry. The meaning of the HSYNCO output in each mode is shown in table 13.9.
Table 13.9 Meaning of HSYNCO Output in Each Mode
Mode
No signal
IHI Signal
HFBACKI
input
S-on-G
mode
CSYNCI
input
Composite HSYNCI
mode
input
Separate HSYNCI
mode
input
IHO Signal
Meaning of IHO Signal
IHI signal (without HFBACKI input is output directly
2fH modification)
IHI signal (with 2fH Meaningless unless there is a double-frequency
modification)
part in the HFBACKI input
CL1 signal
HFBACKI input 1 interval is changed before output
IHG signal
Internal synchronization signal is output
IHI signal (without CSYNCI input (composite synchronization signal)
2fH modification) is output directly
IHI signal (with 2fH Double-frequency part of CSYNCI input (composite
modification)
synchronization signal) is eliminated before output
CL1 signal
CSYNCI input (composite synchronization signal)
horizontal synchronization signal part is separated
before output
IHG signal
Internal synchronization signal is output
IHI signal (without HSYNCI input (composite synchronization signal)
2fH modification) is output directly
IHI signal (with 2fH Double-frequency part of HSYNCI input (composite
modification)
synchronization signal) is eliminated before output
CL1 signal
HSYNCI input (composite synchronization signal)
horizontal synchronization signal part is separated
before output
IHG signal
Internal synchronization signal is output
IHI signal (without HSYNCI input (horizontal synchronization signal) is
2fH modification) output directly
IHI signal (with 2fH Meaningless unless there is a double-frequency
modification)
part in the HSYNCI input (horizontal
synchronization signal)
CL1 signal
HSYNCI input (horizontal synchronization signal) 1
interval is changed before output
IHG signal
Internal synchronization signal is output
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