HD64F2149 Datasheet, PDF (530/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 7
ESTP
0
1
Description
No error stop condition
[Clearing conditions]
1. When 0 is written in ESTP after reading ESTP = 1
2. When the IRIC flag is cleared to 0
• In I²C bus format slave mode
Error stop condition detected
[Setting condition]
When a stop condition is detected during frame transfer
• In other modes
No meaning
(Initial value)
Bit 6—Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been
detected after completion of frame transfer in I²C bus format slave mode.
Bit 6
STOP
0
1
Description
No normal stop condition
(Initial value)
[Clearing conditions]
1. When 0 is written in STOP after reading STOP = 1
2. When the IRIC flag is cleared to 0
• In I²C bus format slave mode
Normal stop condition detected
[Setting condition]
When a stop condition is detected after completion of frame transfer
• In other modes
No meaning
Bit 5—I²C Bus Interface Continuous Transmission/Reception Interrupt Request Flag
(IRTR): Indicates that the I²C bus interface has issued an interrupt request to the CPU, and the
source is completion of reception/transmission of one frame in continuous transmission/reception
for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1
at the same time.
IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically
when the IRIC flag is cleared to 0.
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