HD64F2149 Datasheet, PDF (638/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18B.3 Operation
18B.3.1 Host Interface Activation
The host interface is activated by setting at least one of HICR0 bits LPC3E to LPC1E (bits 7 to 5)
to 1 in single-chip mode. When the host interface is activated, the related I/O ports (ports 37 to 30,
ports 83 and 82) function as dedicated host interface input/output pins. In addition, setting the
FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports 81 and 80, ports
B0 and B1) to the host interface’s input/output pins.
Use the following procedure to activate the host interface after a reset release.
1. Read the signal line status and confirm that the LPC module can be connected. Also check that
the LPC module is initialized internally.
2. When using channel 3, set LADR3 to determine the channel 3 I/O address and whether two-
way registers are to be used.
3. Set the enable bit (LPC3E to LPC1E) for the channel to be used.
4. Set the enable bits (GA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be
used.
5. Set the selection bits for other functions (SDWNE, IEDIR).
6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF). Read IDR or TWR15
to clear IBF.
7. Set interrupt enable bits (IBFIE3 to IBFIE1, ERRIE) as necessary.
18B.3.2 LPC I/O Cycles
There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA
read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and
bus master I/O write. Of these, the chip's HIF:LPC supports only I/O read and I/O write cycles.
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than 0000 in the slave’s synchronization return cycle, but with the H8S/2149’s
HIF:LPC a value of 0000 is always returned.
If the received address matches the host address in an HIF:LPC register (IDR, ODR, STR, TWR),
the host interface enters the busy state; it returns to the idle state by output of a state #12
turnaround. Register (IDR, etc.) and flag (IBF, etc.) changes are made at this timing, so in the
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