HD64F2149 Datasheet, PDF (135/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
CS2E
0
R/W
6
5
4
3
2
1
IOSE INTM1 INTM0 XRST NMIEG HIE
0
0
0
1
0
0
R/W
R
R/W
R
R/W R/W
0
RAME
1
R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI, among other functions.
Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, System
Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of four
interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1.
Bit 5
INTM1
0
1
Bit 4
INTM0
0
1
0
1
Interrupt
Control Mode
0
1
2
3
Description
Interrupts are controlled by I bit
(Initial value)
Interrupts are controlled by I and UI bits and ICR
Cannot be used in the chip
Cannot be used in the chip
Bit 2—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 2
NMIEG
0
1
Description
Interrupt request generated at falling edge of NMI input
Interrupt request generated at rising edge of NMI input
(Initial value)
101