HD64F2149 Datasheet, PDF (528/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

When, with the I²C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The
IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a
retransmission start condition or stop condition after a slave address (SVA) or general call address
match in I²C bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.
The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in
continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the
specified number of ICDR reads or writes have been completed.
Table 16.3 shows the relationship between the flags and the transfer states.
Table 16.3 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL
1/0 1/0 0
0
0
0
0
0
110
0
0
0
0
0
111
0
0
1
0
0
1 1/0 1
0
0
0
0
0
1 1/0 1
0
0
1
0
0
001
0
0
0
1/0 1
001
0
0
0
0
0
001
0
0
0
0
0
001
0
0
0
1
0
0 1/0 1
0
0
0
0
0
0 1/0 1
0
0
1
1
0
011
0
0
0
1
0
0 1/0 0
1/0 1/0 0
0
0
AAS ADZ ACKB State
000
Idle state (flag
clearing required)
000
Start condition
issuance
000
Start condition
established
0 0 0/1 Master mode wait
0 0 0/1 Master mode
transmit/receive end
1/0 1/0 0
Arbitration lost
100
SAR match by first
frame in slave mode
110
General call
address match
000
SARX match
0 0 0/1 Slave mode
transmit/receive end
(except after SARX
match)
000
001
Slave mode
transmit/receive end
(after SARX match)
0 0 0/1 Stop condition
detected
494